In semiconductor-on-insulator (SeOI) type structures, a buried dielectric layer electrically insulates the semiconductor layer from the support substrate.
If the material of the dielectric layer is silicon dioxide (SiO2), the buried dielectric layer is generally designated by the acronym BOX derived from the expression Buried OXide.
In partially depleted (PD) SeOI structures, the thickness of the buried dielectric layer is generally greater than 100 nm and is, therefore, sufficient to ensure the electrical integrity and the quality of the layer.
On the other hand, in fully depleted (FD) SeOI structures, the semiconductor layer and the buried dielectric layer have an ultrathin thickness, i.e., less than 50 nm, possibly as little as around 5 nm.
Such structures are notably intended for the fabrication of transistors, the channel layer being formed in or on the ultrathin semiconductor layer, which is not doped.
Thanks to the ultrathin thickness of the buried dielectric layer and the semiconductor layer, these structures have the advantage of enabling precise control of the channel of the transistor, improving the short channel effect and reducing the variability of the transistor.
The properties of these transistors enable significant reduction of the length of the gate.
Moreover, the ultrathin buried dielectric layer provides improved electrostatic control and the possibility of applying a voltage to the rear face, by means of an electrode arranged on the face of the support substrate opposite the semiconductor layer, for controlling the threshold voltage or adjusting the power/performance trade-off.
In this regard reference may be made to the publications of R. Tsuchiya et al. IEDM Proc., 2007, p. 475 and F. Andrieu et al. VLSI Tech. Proc., 57, 2010.
To be able to apply a voltage to the rear face effectively, the thickness of the buried dielectric layer must be less than 50 nm and preferably 25 nm for transistors based on the fully depleted technology with a size of 28 nm.
Even thinner dielectric layers (down to 5 nm) are expected for future transistor sizes.
However, the very thin buried dielectric layer, which has to withstand a voltage applied to the rear face of the order of a few volts, raises the question of its electrical reliability.
This problem is addressed in the paper by Ishigaki et al. IEEE Trans. Electron. Devices, 58(4), p. 1197, 2011.
An object of the present invention is, thus, to define a method for measuring the electrical quality of the buried dielectric layer with a view to its application in the Fully Depleted technology.
Another object of the invention is to design a method enabling improvement of the electrical properties of the dielectric layer of a semiconductor-on-insulator structure intended to be used in the Fully Deleted technology.